Xgig 16-lane CEM Interposer for PCI Express 5.0

The PCIe 5.0 16-lane CEM Interposer enables debug and verification of new ICs, new system hardware designs, FPGA firmware, validation of system BIOS and software.

Xgig 16-lane CEM Interposer for PCI Express 5.0

The VIAVI Solutions Xgig® 16-lane CEM Interposer for PCI Express® 5.0 enables debug and verification of new ICs, new system hardware designs, FPGA firmware, validation of system BIOS and software—and supports manufacturing test. It provides connection between the VIAVI PCIe 5.0 Analyzer/Exerciser/ Jammer chassis and a system under test. This Interposer installs into a 16-lane PCIe CEM slot which is common on many servers, workstations, and desktop PCs. It operates at the 32GTps, PCIe 5.0 rate, across 16-lanes (bi-directional).

Highlights

  • Supports link widths up to 16-lanes 
  • Operates up to 32GTps, PCIe 5.0 data rates 
  • Downward compatible with PCIe 1.0, 2.0, 3.0 and 4.0, and data rates of 2.5, 5.0, 8.0 and 16GTps 
  • A top edge 16-lane CEM slot connector accepts all endpoint DUT adapter cards 
  • Bottom edge 16-lane PCB finger connector installs into host test system’s 16-lane PCIe slot 
  • Data path uses high-speed linear redrivers to ensure good signal capture with minimal tuning effort 
  • Supports Analyzer side-band signal triggering and capture via custom cable 
  • Interposer power is independent of host system. A 120/220 AC in, 12V/3A DC out converter is included 
  • Custom, exchangeable brackets enable secure chassis and endpoint card installations 
  • LEDs give quick indication of power and operation 
  • Format: Design is based on the 16-lane Card Electro-Mechanical (CEM) specification 
  • Size: 230mm deep x 185mm tall x 15mm thick 

Applications

  • Supported by VIAVI Analyzer tools for trace capture with filter, trigger and more 
  • Supports error injection for deep system analysis
  • Works together with the VIAVI Xgig5PK-PCIe5- X16-PF Analyzer/Exerciser/Jammer chassis platform 

Benefits

  • Provides consistent, repeatable capture of link training, equalization negotiation and other data 

 

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