The Analyzer Interposer installs into an EDSFF slot to provide a fully analog signal path between the root complex and the endpoint. The Analyzer Interposer provides a tap of the data signal communication between host and endpoint devices for input to the Analyzer/Exerciser chassis. It operates at the 64GT/s, PCIe 6.0 rate, across 16-lanes (bi-directional). Variants are available for x16, x8 and x4 lane widths, with accompanying mechanical support for E1.S, E1.L, E3.S, E3.L, and OCP NIC 3.0 modules.
Working together with the VIAVI PCIe 6.0, Analyzer/Exerciser chassis, this Analyzer Interposer enables debug and verification of new ICs, new system hardware designs, FPGA firmware, validation of system BIOS and software, and supports manufacturing test.
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