What is PCIe 5.0?
The 5th generation of Peripheral Component Interconnect Express is known as PCI Express 5.0, or simply PCIe 5.0. First introduced in 2003, PCIe technology has become the standard interface for connecting high-speed components to the motherboard using a point-to-point access bus.
Following a seven-year gap between the completion of PCIe 3.0 and PCIe 4.0, the development and release of the PCI Express 5.0 specification followed quickly on the heels of 4.0 with yet another 2X increase in bandwidth. The finalized PCIe 5.0 standard has been released by PCI-SIG.
PCIe 5.0 Test Tools
Test standards and practices continue to be challenged with each new PCIe release, and PCIe Gen 5 is no exception. The revised EIEOS and clocking features have impacted test practices at the hardware and system levels. Fully downward compatible protocol analyzers capable of supporting 32GT/sec data link speed operations are essential to enabling PCIe 5.0 testing and debugging processes. In addition, superior memory, storage capacity and segmentation for higher volume upstream and downstream traffic capture is required to record long sequences and filter out specific packets for robust protocol analysis.
Alternate protocols, as described in the new PCI Express 5.0 specification, also require support. Equalization options and precoding are more complex for PCIe 5.0, making cutting-edge protocol analyzers with up-to-date feature sets an invaluable asset.
Jamming capability remains essential to test coverage, as the simulation of network traffic in real time creates an important litmus test for PCIe hardware. Intelligent and protocol aware jammers such as the Xgig Jammer support PCIe 5.0 test setup inline operation, automated discovery and regression testing, as well as test support over a wide range of protocols.
PCIe 5.0 Release Date
The release of the PCI Express 5.0 standard on May 29, 2019 was the culmination of an accelerated 18-month development cycle deemed necessary to address the escalating performance demands of data-intensive applications.
Like all previous generations, PCIe 5.0 maintains backwards compatibility with past iterations, although the lowest version (speed) between the PCIe slot and connecting card remains the gating factor. In addition to the bandwidth increase, the 5.0 standard also includes electrical enhancements to improve signal integrity and mechanical updates to improve connector performance.
Although the final release of PCIe 4.0 was completed in June of 2017, the commercialization of requisite components remains in its early stages. The timing of the PCIe 5.0 release provides a unique “leap-frogging” option that empowers hardware manufacturers to forego PCIe 4.0 entirely. A direct transition from PCIe 3.0 to 5.0 produces a 4X “speed bump”, with a PCIe 5.0 x4 slot delivering the same bandwidth performance as a PCIe 3.0 x16 full-size slot, thereby freeing up valuable connection real estate.
As has been the case with each successive PCIe release, a coexistence between PCIe Express 5.0 and 4.0 allows the most demanding high-performance applications, such as cloud computing and AI, to take advantage of the highest available transfer rates.
PCIe Gen 5 Speed
The speed doubling convention of PCIe remains consistent with the release of PCIe 5.0. Using the same 128b/130b encoding method that has been standard since PCIe 3.0, PCIe 5.0 will deliver 64 GB/sec of throughput in each direction. Since PCIe technology allows data to flow full duplex bidirectionally, the total throughput for both directions combined amounts to 128 GB/sec.
The encoding standard prior to PCIe 3.0 was 8b/10b, meaning eight bits of data were encoded and transmitted as a 10-bit number. This in turn created a 20% performance overhead factor that reduced a raw bit transfer rate of 2.5 GT/sec to a net bandwidth of just 2.0 Gbit/sec. This more efficient 1.5% overhead factor remains in effect with the PCIe 5.0 encoding convention.
The phenomenal speed of PCIe 5.0 enables the equivalent of a typical Blu-ray disc contents to be transferred to non-volatile memory (NVM) in under one second. Although this exceptional speed may seem like a luxury, it has been necessitated by enhancements to network architecture in other arenas. For example, 400G Ethernet requires 50 GB/sec of bandwidth in each direction to interface with the CPU at maximum capacity.
With PCIe 4.0, the 32 GB/sec available on a full size x16 slot proved to be insufficient. Using PCIe 5.0 technology, the available bandwidth exceeds the requirements of this interface with room to spare.
In addition to Ethernet, artificial intelligence (AI), gaming, high-volume external storage and cloud computing are some of the many applications that can maximize the potential of PCIe Gen 5 speed and bandwidth. Individual users of multi-GPU systems and premium graphics cards also reap tangible benefits from PCIe 5.0 speed enhancement.
PCI Express 5.0 Specification
The PCI Express 5.0 specification might be classified as a natural evolution of the backwards compatible PCIe standard with no inherent link or transaction layer changes included in this iteration. The 5.0 specification continues the trend toward extended tags and credits established with PCIe 4.0.
A new CEM connector designated for add-in cards has been added. In addition, improvements to signal integrity and connector design features have improved overall performance and reliability. Physical layer enhancements also include an update to the Electrical Idle Exit Ordered Set (EIEOS), SKP ordered sets and equalization sequences.
The PCI Express 5.0 specification has been generally lauded by hardware manufacturers and industry insiders. In particular, the elimination of the I/O bottleneck, enabling of 5G and cloud innovation and reduced noise, have been cited as exceptional PCIe 5.0 characteristics. This industry consensus, along with the relatively benign set of implementation prerequisites required to transition from 4.0 to 5.0, have spearheaded aggressive hardware development and commercialization targets.
PCIe 5.0 Challenges
Signal loss remains an ongoing architectural challenge with PCIe 5.0. Retimers, redrivers and alternate printed circuit board (PCB) base materials are some of the cost/benefit options available to hardware designers to mitigate these concerns. A retimer can be used to retransmit the signal or a redriver can be used to amplify it, with either method improving the physical reach of the link.
The insertion loss inherent to PCIe technology continues with the PCIe 5.0 release, so board loss inherent to FR4 PCB construction is no longer tenable and alternate materials like Megtron have become compulsory. New equalization circuit designs for the transmitter (TX) and receiver (RX) have also been necessitated by the channel requirements for PCIe 5.0.
PCIe 5 vs PCIe 4
In making the jump from PCIe 4.0 to PCI Express 5.0, speed doubling, backwards compatibility and an accelerated release cycle were three essential pillars upon which the implementation strategy was constructed.
New features that enabled or supported the speed increase were prioritized over other recommended or requested changes. For example, the EIEOS and data bit rate definition changes were required to enable the speed increase, but fundamental PCIe elements such as the encoding method and target bit error rate (BER) remained constant.
Despite the emphasis on time-to-market and compatibility, other important design changes between PCIe 4.0 and 5.0 impacted mating hardware and test practices. These included clock data recovery (CDR) with a second-order response and a CEM connector that is only compatible with a surface mount PCBA footprint, although it remains backwards compatible at the add-in card interface. PCI Express 5.0 also supports alternate protocols, through modified TS1/TS2 sequences.
Consistency between PCIe 4.0 and PCIe 5.0 standards was further necessitated by the unusually long release time for the 4.0 standard, as the network landscape and bandwidth demand continued to unfold in the background. This has virtually assured an overlap period between the two standards, making commonality in design and test practices essential for a smooth transition.
The Future of PCIe 5.0
The breakneck cadence of PCIe release dates seems destined to continue with the final specification release for PCIe 6.0 expected in 2021. This new iteration will continue the traditional bandwidth doubling and backwards compatibility that have signified the PCIe standard, this time reaching a staggering 256 GB/sec of bidirectional bandwidth. This will effectively put PCIe on par with the VRAM bandwidth of a low-end GPU. To enable yet another two-fold speed increase, pulse amplitude modulation (PAM4) with forward error correction (FEC) technology will be incorporated. The IoT and self-driving vehicles are potential beneficiaries of this enhancement, as their performance relies upon rapid access to multiple peripherals simultaneously.
PCIe Express 5.0 is yet another successful leap in I/O bussing technology, keeping pace with Moore’s law while shedding the network architecture bottleneck mantel for the foreseeable future. With new and improved PCIe 5.0 test tools arriving every day, this progress should continue successfully through the release of PCIe 6.0 and many future generations to come.
Discover PCIe with VIAVI today!
Are you ready to take the next step with one of our PCIe products or solutions?
Complete one of the following forms to get going: