Guide to PCIe - Peripheral Component Interconnect Express
Peripheral Component Interconnect Express, commonly known as PCI Express and abbreviated as “PCIe”, is a high speed computer bus architecture which has become the industry standard for nearly all internal computer component connections.
PCIe provides the connections from a computer’s processor(s) and memory to other components and peripherals. This interface is a highspeed serial transport designed to replace older parallel bus architectures including PCI and ISA (Industry Standard Architecture). PCIe uses a point-to-point access bus that provides outstanding data transfer speed improvement over its predecessors.
In the 1980’s, early computer bus architecture was based on parallel data paths between the CPU and all components.
By the late 1990’s, the predecessors of PCIe, had been developed, integrating the familiar form factor of connecting device cards sliding into corresponding locations on the motherboard. The PCI bus came in 32-bit and 64-bit versions, while the AGP (Accelerated Graphics Port) was developed specifically for graphic controller connections with greater bandwidth needs than the PCI bus could provide. Today both interfaces have largely been supplanted by PCI Express.
What Does PCIe Mean?
By the early 2000’s, demands on computing bandwidth by internal hardware and peripherals had led to the next generation of PCI, known as PCI Express, or PCIe. The biggest advantage of PCIe over conventional PCI is that it utilizes a serial interface, rather than the parallel interface used in PCI architecture. Another advantage is the use of individual, rather than shared busses, for each connected device.
Data transfer is further enhanced with the utilization of multiple lanes for the connected devices that require them. Defined by the number of data port connections assigned, each increase in lanes, i.e. x1 (by 1) to x16 (by 16), represents a corresponding increase in data transfer volume. Now the passengers headed from point A to point B can ride on multiple busses simultaneously, if the capacity demand requires it.
With the widespread acceptance and popularity of PCIe as the de facto standard, a variety of functional components have adopted this platform, including USB, Bluetooth and video cards. Video controllers and storage devices are examples of technologies that have been enabled by the advent of PCIe architecture. This is evidenced by the improved graphics and computer performance we have experienced over the past decade.
The breakthroughs included in PCI Express architecture have enabled substantially faster transfer rates, as compared to PCI, and each successive version of PCIe has continued to build upon these improvements. Whereas conventional PCI utilized common address, data and control lines, the point to point topology of PCIe provides separate links to each connected device, freeing each from the potential constraints of the others.
PCIe communication utilizes a mode of data transfer known as “packets”. The transaction layer of the PCIe port performs the task of packetizing and de-packetizing the data. This difference in electrical signaling inherent to PCIe vs. conventional PCI required distinct electronic and connector architecture to be developed, making PCIe slots incompatible with PCI cards.
PCIE Architecture – Inside Server
NVME Over Fabrics – Outside Architecture
A variety of formats have been developed for PCI Express, each with slightly different nomenclature. Understanding what these PCIe formats indicate in terms of size and version is essential information for understanding what expansion cards will (or will not) work with your system.
Since the introduction of PCIe 1.0 in 2002, successive versions have been introduced to meet the growing demands for more bandwidth and frequency. Version 1.0 had an available bandwidth of just under 8GB/sec for the combined 16 lanes of traffic. The frequency for PCIe 1.0 was 2.5 GHz. With each new version, the total bandwidth has doubled, while the frequency for PCIe 4.0, introduced in 2017, has increased to 16 GHz to go along with 64GB/sec of bandwidth. This “doubling” convention will continue with PCIe 5.0, to be released in 2019. Along with performance improvements, each version has provided new features and increased energy efficiency.
With a lofty standard of doubling bandwidth every few years to avoid becoming the bottleneck, as processor speed and memory continues to increase rapidly, each revision provides a new challenge for designers. Potential for crosstalk and electrical discontinuity increases along with bandwidth, so new materials and design innovations continue to push the envelope.
The size of any PCI Express card, as well as the number of pins, is dictated by the number of lanes and total connections. The same holds true for all PCIe versions. Available PCIe sizes and their corresponding pin counts are as follows.
|PCI Express x1||25mm||18 pins|
|PCI Express x4||39mm||32 pins|
|PCI Express x8||56mm||49 pins|
|PCI Express x16||89mm||82 pins|
Unlike PCI cards, a PCI Express card may be installed in any size PCIe slot, as long as the slot is at least as large, if not larger than, the card. This means an x1 expansion card can be installed in an x1, x4, x8 or x16 slot. The same applies in reverse, meaning you can install an x16 card into an x4 slot, for example, but only if the slot is the type configured with its rear side open. In this case, however, the bandwidth would be limited to that of an x4 card.
The bandwidth available to the PCIe card is driven by the revision of the CPU or motherboard PCIe controller, meaning a version 3.0 card will only operate at the bandwidth of a version 2.0 card, if the controller was configured for version 2.0.
The Future of PCIe
The immediate future of PCI Express will be determined by the upcoming release of PCIe 5.0 in 2019. This new revision, like its predecessors, will double the available bandwidth of the current version 4.0. In addition to the performance upgrade, physical differences inherent to PCIe 5.0 will include shorter keys and integration of improved materials on the printed circuit board. PCIe 5.0 will remain backwards compatible with PCIe 3.0 and 4.0. For this reason, motherboards and adapter cards will not require immediate upgrades. As computer hardware designers and manufacturers continue to integrate PCIe into their latest offerings, the entrenched position of de facto standard becomes more secure.
Computing power and memory enhancements continue to evolve at breakneck speed. So far, the PCI Express bus has managed to keep pace, but the gap is narrowing. Data transfer innovations in the not-so-distant future may seem like a Hyperloop compared to our familiar and reliable bus, and necessarily so. Perhaps no computer technology plays as important a role in meeting the demand for speed and bandwidth, so the impetus on designers for ongoing breakthroughs in PCIe performance will continue into the foreseeable future.